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CS5346
103 dB, 192 kHz, Stereo Audio ADC with 6:1 Input Mux
ADC Features
Multi-bit Delta Sigma Modulator 103 dB Dynamic Range -95 dB THD+N Stereo 6:1 Input Multiplexer Programmable Gain Amplifier (PGA) - 12 dB Gain, 0.5 dB Step Size - Zero-crossing, Click-free Transitions Stereo Microphone Inputs - +32 dB Gain Stage - Low-noise Bias Supply Up to 192 kHz Sampling Rates Selectable 24-bit, Left-justified or IS Serial Audio Interface Formats
General Description
The CS5346 integrates an analog multiplexer, programmable gain amplifier, and stereo audio analog-to-digital converter. The CS5346 performs stereo analog-to-digital (A/D) conversion of 24-bit serial values at sample rates up to 192 kHz. A 6:1 stereo input multiplexer is included for selecting between line-level and microphone-level inputs. The microphone input path includes a +32 dB gain stage and a low-noise bias voltage supply. The PGA is available for line or microphone inputs and provides gain/attenuation of 12 dB in 0.5 dB steps. The output of the PGA is followed by an advanced 5thorder, multi-bit delta sigma modulator and digital filtering/decimation. Sampled data is transmitted by the serial audio interface at rates from 8 kHz to 192 kHz in either Slave or Master Mode. Integrated level translators allow easy interfacing between the CS5346 and other devices operating over a wide range of logic levels. The CS5346 is available in a 48-pin LQFP package in Commercial (-40 to +85 C) and Automotive (-40 to +105 C) grades. The CDB5346 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please refer to "Ordering Information" on page 40 for complete details.
System Features
Power-down Mode +5 V Analog Power Supply, Nominal +3.3 V Digital Power Supply, Nominal Direct Interface with 3.3 V to 5 V Logic Levels Pin Compatible with CS5345* *See Section 2. on page 7 for more details.
3.3 V to 5 V
3.3 V
5V
Level Translator
IC /SPITM Control Data Interrupt Overflow Reset
(R)
Left PGA Output Register Configuration PCM Serial Interface Internal Voltage Reference Right PGA Output Stereo Input 1 Stereo Input 2 Stereo Input 3 PGA MUX PGA
+32 dB
High Pass Filter
Low-Latency Anti-Alias Filter
Multibit Oversampling ADC Multibit Oversampling ADC
Serial Audio Output
Level Translator
Stereo Input 4 / Mic Input 1 & 2
+32 dB
High Pass Filter
Low-Latency Anti-Alias Filter
Stereo Input 5 Stereo Input 6
Preliminary Product Information
http://www.cirrus.com
This document contains information for a product under development. Cirrus Logic reserves the right to modify this product without notice.
Copyright (c) Cirrus Logic, Inc. 2008 (All Rights Reserved)
NOVEMBER `08 DS861PP1
CS5346
TABLE OF CONTENTS
1. PIN DESCRIPTIONS - CS5346 ............................................................................................................. 5 2. PIN COMPATIBILITY - CS5345/CS5346 DIFFERENCES ..................................................................... 7 3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 8 RECOMMENDED OPERATING CONDITIONS ................................................................................... 8 ABSOLUTE MAXIMUM RATINGS ....................................................................................................... 8 ANALOG CHARACTERISTICS (COMMERCIAL) ................................................................................ 9 ANALOG CHARACTERISTICS (COMMERCIAL) CONT. .................................................................. 10 ANALOG CHARACTERISTICS (AUTOMOTIVE) ............................................................................... 11 ANALOG CHARACTERISTICS (AUTOMOTIVE) CONT. ................................................................... 12 DIGITAL FILTER CHARACTERISTICS .............................................................................................. 13 DC ELECTRICAL CHARACTERISTICS ............................................................................................. 14 DIGITAL INTERFACE CHARACTERISTICS ...................................................................................... 15 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT ............................................................. 16 SWITCHING CHARACTERISTICS - CONTROL PORT - IC FORMAT ............................................ 18 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ........................................... 19 4. TYPICAL CONNECTION DIAGRAM ................................................................................................... 20 5. APPLICATIONS ................................................................................................................................... 21 5.1 Recommended Power-Up Sequence ............................................................................................. 21 5.2 System Clocking ............................................................................................................................. 21 5.2.1 Master Clock ......................................................................................................................... 21 5.2.2 Master Mode ......................................................................................................................... 22 5.2.3 Slave Mode ........................................................................................................................... 22 5.3 High-Pass Filter and DC Offset Calibration .................................................................................... 22 5.4 Analog Input Multiplexer, PGA, and Mic Gain ................................................................................ 23 5.5 Input Connections ........................................................................................................................... 23 5.5.1 Analog Input Configuration for 1 VRMS Input Levels ............................................................ 23 5.5.2 Analog Input Configuration for 2 VRMS Input Levels ............................................................ 24 5.6 PGA Auxiliary Analog Output ......................................................................................................... 25 5.7 Control Port Description and Timing ............................................................................................... 25 5.7.1 SPI Mode ............................................................................................................................... 25 5.7.2 IC Mode ................................................................................................................................ 26 5.8 Interrupts and Overflow .................................................................................................................. 27 5.9 Reset .............................................................................................................................................. 28 5.10 Synchronization of Multiple Devices ............................................................................................. 28 5.11 Grounding and Power Supply Decoupling .................................................................................... 28 6. REGISTER QUICK REFERENCE ........................................................................................................ 29 7. REGISTER DESCRIPTION .................................................................................................................. 30 7.1 Chip ID - Register 01h .................................................................................................................... 30 7.2 Power Control - Address 02h ......................................................................................................... 30 7.2.1 Freeze (Bit 7) ......................................................................................................................... 30 7.2.2 Power-Down MIC (Bit 3) ........................................................................................................ 30 7.2.3 Power-Down ADC (Bit 2) ....................................................................................................... 30 7.2.4 Power-Down Device (Bit 0) ................................................................................................... 30 7.3 ADC Control - Address 04h ............................................................................................................ 31 7.3.1 Functional Mode (Bits 7:6) .................................................................................................... 31 7.3.2 Digital Interface Format (Bit 4) .............................................................................................. 31 7.3.3 Mute (Bit 2) ............................................................................................................................ 31 7.3.4 High-Pass Filter Freeze (Bit 1) .............................................................................................. 31 7.3.5 Master / Slave Mode (Bit 0) ................................................................................................... 31 7.4 MCLK Frequency - Address 05h .................................................................................................... 32 7.4.1 Master Clock Dividers (Bits 6:4) ............................................................................................ 32 7.5 PGAOut Control - Address 06h ...................................................................................................... 32 2 DS861PP1
CS5346
7.5.1 PGAOut Source Select (Bit 6) ............................................................................................... 32 7.6 Channel B PGA Control - Address 07h .......................................................................................... 32 7.6.1 Channel B PGA Gain (Bits 5:0) ............................................................................................. 32 7.7 Channel A PGA Control - Address 08h .......................................................................................... 33 7.7.1 Channel A PGA Gain (Bits 5:0) ............................................................................................. 33 7.8 ADC Input Control - Address 09h ................................................................................................... 33 7.8.1 PGA Soft Ramp or Zero Cross Enable (Bits 4:3) .................................................................. 33 7.8.2 Analog Input Selection (Bits 2:0) ........................................................................................... 34 7.9 Active Level Control - Address 0Ch ................................................................................................ 34 7.9.1 Active High/ Low (Bit 0) ......................................................................................................... 34 7.10 Status - Address 0Dh ................................................................................................................... 34 7.10.1 Clock Error (Bit 3) ................................................................................................................ 35 7.10.2 Overflow (Bit 1) .................................................................................................................... 35 7.10.3 Underflow (Bit 0) .................................................................................................................. 35 7.11 Status Mask - Address 0Eh .......................................................................................................... 35 7.12 Status Mode MSB - Address 0Fh ................................................................................................. 35 7.13 Status Mode LSB - Address 10h .................................................................................................. 35 8. PARAMETER DEFINITIONS ................................................................................................................ 36 9. FILTER PLOTS ..................................................................................................................................... 37 10. PACKAGE DIMENSIONS .................................................................................................................. 39 11. THERMAL CHARACTERISTICS AND SPECIFICATIONS .............................................................. 39 12. ORDERING INFORMATION .............................................................................................................. 40 13. REVISION HISTORY .......................................................................................................................... 40
LIST OF FIGURES
Figure 1.Master Mode Serial Audio Port Timing ....................................................................................... 17 Figure 2.Slave Mode Serial Audio Port Timing ......................................................................................... 17 Figure 3.Format 0, 24-Bit Data Left-Justified ............................................................................................ 17 Figure 4.Format 1, 24-Bit Data IS ............................................................................................................ 17 Figure 5.Control Port Timing - IC Format ................................................................................................. 18 Figure 6.Control Port Timing - SPI Format ................................................................................................ 19 Figure 7.Typical Connection Diagram ....................................................................................................... 20 Figure 8.Master Mode Clocking ................................................................................................................ 22 Figure 9.Analog Input Architecture ............................................................................................................ 23 Figure 10.CS5346 PGA ............................................................................................................................ 24 Figure 11.1 VRMS Input Circuit .................................................................................................................. 24 Figure 12.1 VRMS Input Circuit with RF Filtering ....................................................................................... 24 Figure 13.2 VRMS Input Circuit .................................................................................................................. 24 Figure 14.Control Port Timing in SPI Mode .............................................................................................. 26 Figure 15.Control Port Timing, IC Write ................................................................................................... 26 Figure 16.Control Port Timing, IC Read ................................................................................................... 27 Figure 17.Single-Speed Stopband Rejection ............................................................................................ 37 Figure 18.Single-Speed Stopband Rejection ............................................................................................ 37 Figure 19.Single-Speed Transition Band (Detail) ...................................................................................... 37 Figure 20.Single-Speed Passband Ripple ................................................................................................ 37 Figure 21.Double-Speed Stopband Rejection ........................................................................................... 37 Figure 22.Double-Speed Stopband Rejection ........................................................................................... 37 Figure 23.Double-Speed Transition Band (Detail) .................................................................................... 38 Figure 24.Double-Speed Passband Ripple ............................................................................................... 38 Figure 25.Quad-Speed Stopband Rejection ............................................................................................. 38 Figure 26.Quad-Speed Stopband Rejection ............................................................................................. 38 Figure 27.Quad-Speed Transition Band (Detail) ....................................................................................... 38 Figure 28.Quad-Speed Passband Ripple ................................................................................................. 38 DS861PP1 3
CS5346
LIST OF TABLES
Table 1. Speed Modes .............................................................................................................................. 21 Table 2. Common Clock Frequencies ....................................................................................................... 21 Table 3. Slave Mode Serial Bit Clock Ratios ............................................................................................. 22 Table 4. Device Revision .......................................................................................................................... 30 Table 5. Freeze-able Bits .......................................................................................................................... 30 Table 6. Functional Mode Selection .......................................................................................................... 31 Table 7. Digital Interface Formats ............................................................................................................. 31 Table 8. MCLK Frequency ........................................................................................................................ 32 Table 9. PGAOut Source Selection ........................................................................................................... 32 Table 10. Example Gain and Attenuation Settings ................................................................................... 33 Table 11. PGA Soft Cross or Zero Cross Mode Selection ........................................................................ 34 Table 12. Analog Input Multiplexer Selection ............................................................................................ 34
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CS5346 1. PIN DESCRIPTIONS - CS5346
OVFL
SDOUT
DGND
MCLK
LRCK
SCLK
INT
NC
NC
NC
48 47 46 45 44 43 42 41 40 39 38 37
SDA/CDOUT SCL/CCLK AD0/CS AD1/CDIN VLC RST AIN3A AIN3B AIN2A AIN2B AIN1A AIN1B
NC
VD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
FILT+ VQ VQ NC AIN4A/MICIN1 AIN4B/MICIN2 AGND AFILTA AFILTB VA AIN5A AIN5B
36 35 34 33 32
VLS NC NC NC AGND NC NC PGAOUTB PGAOUTA AIN6B AIN6A MICBIAS
CS5346
31 30 29 28 27 26 25
Pin Name
SDA/CDOUT SCL/CCLK AD0/CS AD1/CDIN VLC RST AIN3A AIN3B AIN2A AIN2B
#
1 2 3 4 5 6 7 8 9 10
Pin Description
Serial Control Data (Input/Output) - SDA is a data I/O in IC(R) Mode. CDOUT is the output data line for the control port interface in SPITM Mode. Serial Control Port Clock (Input) - Serial clock for the serial control port. Address Bit 0 (IC) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in IC Mode; CS is the chip-select signal for SPI format. Address Bit 1 (IC) / Serial Control Data Input (SPI) (Input) - AD1 is a chip address pin in IC Mode; CDIN is the input data line for the control port interface in SPI Mode. Control Port Power (Input) - Determines the required signal level for the control port interface. Refer to the Recommended Operating Conditions for appropriate voltages. Reset (Input) - The device enters a low-power mode when this pin is driven low. Stereo Analog Input 3 (Input) - The full-scale level is specified in the Analog Characteristics specification table. Stereo Analog Input 2 (Input) - The full-scale level is specified in the Analog Characteristics specification table.
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CS5346
AIN1A AIN1B AGND VA AFILTA AFILTB VQ FILT+ NC AIN4A/MICIN1 AIN4B/MICIN2 AIN5A AIN5B MICBIAS AIN6A AIN6B PGAOUTA PGAOUTB NC AGND NC 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Stereo Analog Input 1 (Input) - The full-scale level is specified in the Analog Characteristics specification table. Analog Ground (Input) - Ground reference for the internal analog section. Analog Power (Input) - Positive power for the internal analog section. Anti-alias Filter Connection (Output) - Antialias filter connection for the channel A ADC input. Anti-alias Filter Connection (Output) - Antialias filter connection for the channel B ADC input. Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. No Connect - This pin is not connected internally and should be tied to ground to minimize any potential coupling effects. Stereo Analog Input 4 / Microphone Input 1 & 2 (Input) - The full-scale level is specified in the Analog Characteristics specification table. Stereo Analog Input 5 (Input) - The full-scale level is specified in the Analog Characteristics specification table. Microphone Bias Supply (Output) - Low-noise bias supply for external microphone. Electrical characteristics are specified in the DC Electrical Characteristics specification table. Stereo Analog Input 6 (Input) - The full-scale level is specified in the Analog Characteristics specification table. PGA Analog Audio Output (Output) - Either an analog output from the PGA block or high impedance. See "PGAOut Source Select (Bit 6)" on page 32. No Connect - These pins are not connected internally and should be tied to ground to minimize any potential coupling effects. Analog Ground (Input) - Ground reference for the internal analog section. No Connect - These pins are not connected internally and should be tied to ground to minimize any potential coupling effects. Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio interface. Refer to the Recommended Operating Conditions for appropriate voltages. No Connect - These pins are not connected internally and should be tied to ground to minimize any potential coupling effects. Serial Audio Data Output (Output) - Output for two's complement serial audio data. Serial Clock (Input/Output) - Serial clock for the serial audio interface. Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. Master Clock (Input) - Clock source for the ADC's delta-sigma modulators. Digital Ground (Input) - Ground reference for the internal digital section. Digital Power (Input) - Positive power for the internal digital section. Interrupt (Output) - Indicates an interrupt condition has occurred. Overflow (Output) - Indicates an ADC overflow condition is present.
VLS
NC
SDOUT SCLK LRCK MCLK DGND VD INT OVFL
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CS5346 2. PIN COMPATIBILITY - CS5345/CS5346 DIFFERENCES
The CS5346 is pin compatible with the CS5345 and is a drop in replacement for CS5345 applications where VA = 5 V, VD = 3.3 V, VLS 3.3 V, and VLC 3.3 V. The pinout diagram and table below show the requirements for the remaining pins when replacing the CS5345 in these designs with a CS5346.
OVFL SDOUT DGND MCLK LRCK SCLK TSTI
INT
NC
NC
48 47 46 45 44 43 42 41 40 39 38 37
SDA/CDOUT SCL/CCLK AD0/CS AD1/CDIN VLC RST AIN3A AIN3B AIN2A AIN2B AIN1A AIN1B
NC
VD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
AIN4A/MICIN1 AIN4B/MICIN2 AFILTA AFILTB AGND FILT+ TSTI VA AIN5A AIN5B TSTO VQ
36 35 34 33
VLS TSTO NC NC AGND AGND VA PGAOUTB PGAOUTA AIN6B AIN6A MICBIAS
CS5345 Compatibility
32 31 30 29 28 27 26 25
#
5 14 18 20 30 31 35 36 37 46
CS5345 Pin Name
VLC VA TSTO TSTI VA AGND TSTO VLS TSTI VD
CS5346 Pin Name
VLC VA VQ NC NC NC NC VLS NC VD
CS5346 Connection for Compatibility
Control Port Power (Input) -Limited to nominal 5 or 3.3 V. Analog Power (Input) - Limited to nominal 5 V. This pin must be left unconnected. This pin should be tied to ground. This pin may be connected to the analog supply voltage. The decoupling capacitor for the CS5345 is not required. This pin should be connected to ground. This pin may be left unconnected. Serial Audio Interface Power (Input) - Limited to nominal 5 or 3.3 V. This pin should be tied to ground. Digital Power (Input) - Limited to nominal 3.3 V
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CS5346 3. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS
AGND = DGND = 0 V; All voltages with respect to ground. Parameters
Analog Digital Logic - Serial Port Logic - Control Port Ambient Operating Temperature (Power Applied) Commercial Automotive DC Power Supplies:
Symbol
VA VD VLS VLC TA TA
Min
4.75 3.13 3.13 3.13 -40 -40
Nom
5.0 3.3 3.3 3.3 -
Max
5.25 3.47 5.25 5.25 +85 +105
Units
V V V V C C
ABSOLUTE MAXIMUM RATINGS
AGND = DGND = 0 V All voltages with respect to ground. (Note 1) Parameter
DC Power Supplies: Analog Digital Logic - Serial Port Logic - Control Port (Note 2) Logic - Serial Port Logic - Control Port
Symbol
VA VD VLS VLC Iin VINA VIND-S VIND-C TA Tstg
Min
-0.3 -0.3 -0.3 -0.3 AGND-0.3 -0.3 -0.3 -50 -65
Max
+6.0 +3.63 +6.0 +6.0 10 VA+0.3 VLS+0.3 VLC+0.3 +125 +150
Units
V V V V mA V V V C C
Input Current Analog Input Voltage Digital Input Voltage Ambient Operating Temperature (Power Applied) Storage Temperature
Notes:
1. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 2. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SCR latch-up.
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CS5346 ANALOG CHARACTERISTICS (COMMERCIAL)
Test conditions (unless otherwise specified): VA = 5 V; VD = VLS = VLC = 3.3 V; AGND = DGND = 0 V; TA = +25 C; Input test signal: 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Fs = 48/96/192 kHz; PGA gain = 0 dB; All connections as shown in Figure 7 on page 20.
Parameter Analog-to-Digital Converter Characteristics
Dynamic Range (Line Level Inputs)
Symbol
Min
Typ
Max
Unit
A-weighted 97 103 unweighted 94 100 (Note 3) 40 kHz bandwidth unweighted 98 Total Harmonic Distortion + Noise (Line Level Inputs) (Note 4) -1 dB -95 -89 -20 dB THD+N -80 -40 -60 dB (Note 3) 40 kHz bandwidth -1 dB -92 Dynamic Range (Mic Level Inputs) A-weighted 77 83 (Note 3) unweighted 74 80 Total Harmonic Distortion + Noise (Mic Level Inputs) (Note 4) -80 -74 -1 dB THD+N -20 dB -60 -20 (Note 3) -60 dB Interchannel Isolation (Line Level Inputs) 90 (Mic Level Inputs) 80 A/D Full-scale Input Voltage 0.51*VA 0.57*VA 0.63*VA Gain Error 10 Interchannel Gain Mismatch 0.1 -
dB dB dB dB dB dB dB dB dB dB dB dB dB dB Vpp % dB dB V/V dB k
Microphone - Level Input Characteristics
Preamplifier Gain Interchannel Gain Mismatch Input Impedance 31 35.5 32 40 0.1 60 33 44.7 -
(Note 5)
3. Valid for Double- and Quad-Speed Modes only. 4. Referred to the typical A/D full-scale input voltage 5. Valid when the microphone-level inputs are selected.
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CS5346 ANALOG CHARACTERISTICS (COMMERCIAL) CONT.
Parameter Line-Level Input and Programmable Gain Amplifier
Gain Range Gain Step Size Absolute Gain Step Error Maximum Input Level Input Impedance Selected inputs Un-selected inputs Selected Interchannel Input Impedance Mismatch
Symbol
Min
- 12 -4 28.8 -
Typ
0.5 36 5
Max
+ 12 +4 0.4 0.85*VA 43.2 38 -
Unit
dB V/V dB dB Vpp k k %
Analog Outputs
Dynamic Range (Line Level Inputs) A-weighted unweighted (Note 6) -1 dB THD+N -20 dB -60 dB A-weighted unweighted (Note 6) -1 dB THD+N -20 dB -60 dB 98 95 77 74 -0.1dB 100 104 101 -80 -81 -41 83 80 -74 -60 -20 180 -74 -68 +0.1dB 1 20 dB dB dB dB dB dB dB dB dB dB dB deg A k pF
Total Harmonic Distortion + Noise (Line Level Inputs)
Dynamic Range (Mic Level Inputs)
Total Harmonic Distortion + Noise (Mic Level Inputs)
Frequency Response 10 Hz to 20 kHz Analog In to Analog Out Phase Shift DC Current draw from a PGAOUT pin AC-Load Resistance Load Capacitance
IOUT RL CL
6. Referred to the typical A/D Full-Scale Input Voltage.
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CS5346 ANALOG CHARACTERISTICS (AUTOMOTIVE)
Test conditions (unless otherwise specified): VA = 5.0 V +/- 5%; VD = VLS = VLC = 3.3 V +/- 5%; AGND = DGND = 0 V; TA = -40 to +85 C; Input test signal: 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Fs = 48/96/192 kHz; PGA gain = 0 dB; All connections as shown in Figure 7 on page 20.
Parameter Analog-to-Digital Converter Characteristics
Dynamic Range (Line Level Inputs)
Symbol
Min
Typ
Max
Unit
A-weighted 95 103 unweighted 92 100 (Note 3) 40 kHz bandwidth unweighted 98 Total Harmonic Distortion + Noise (Line Level Inputs) (Note 4) -1 dB -95 -87 -20 dB THD+N -80 -40 -60 dB (Note 3) 40 kHz bandwidth -1 dB -92 Dynamic Range (Mic Level Inputs) A-weighted 75 83 (Note 3) unweighted 72 80 Total Harmonic Distortion + Noise (Mic Level Inputs) (Note 4) -80 -72 -1 dB THD+N -20 dB -60 -20 (Note 3) -60 dB Interchannel Isolation (Line Level Inputs) 90 (Mic Level Inputs) 80 A/D Full-scale Input Voltage 0.51*VA 0.57*VA 0.63*VA Gain Error 10 Interchannel Gain Mismatch 0.1 -
dB dB dB dB dB dB dB dB dB dB dB dB dB dB Vpp % dB dB V/V dB k
Microphone - Level Input Characteristics
Preamplifier Gain Interchannel Gain Mismatch Input Impedance 31 35.48 32 40 0.1 60 33 44.67 -
(Note 5)
7. Valid for Double- and Quad-Speed Modes only. 8. Referred to the typical A/D full-scale input voltage 9. Valid when the microphone-level inputs are selected.
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CS5346 ANALOG CHARACTERISTICS (AUTOMOTIVE) CONT.
Parameter Line-Level Input and Programmable Gain Amplifier
Gain Range Gain Step Size Absolute Gain Step Error Maximum Input Level Input Impedance Selected inputs Un-selected inputs Selected Interchannel Input Impedance Mismatch
Symbol
Min
- 12 -4 28.8 -
Typ
0.5 36 5
Max
+ 12 +4 0.4 0.85*VA 43.2 38 -
Unit
dB V/V dB dB Vpp k k %
Analog Outputs
Dynamic Range (Line Level Inputs) A-weighted unweighted (Note 6) -1 dB THD+N -20 dB -60 dB A-weighted unweighted (Note 6) -1 dB THD+N -20 dB -60 dB 96 93 77 74 -0.1dB 100 104 101 -80 -81 -41 83 80 -74 -60 -20 180 -74 -68 +0.1dB 1 20 dB dB dB dB dB dB dB dB dB dB dB deg A k pF
Total Harmonic Distortion + Noise (Line Level Inputs)
Dynamic Range (Mic Level Inputs)
Total Harmonic Distortion + Noise (Mic Level Inputs)
Frequency Response 10 Hz to 20 kHz Analog In to Analog Out Phase Shift DC Current draw from a PGAOUT pin AC-Load Resistance Load Capacitance
IOUT RL CL
10. Referred to the typical A/D Full-Scale Input Voltage.
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CS5346 DIGITAL FILTER CHARACTERISTICS
Parameter (Note 11) Single-Speed Mode
Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) tgd (-0.1 dB) 0 0.5688 70 0 0.5604 69 tgd 0 0.5000 60 tgd (Note 12) (Note 12) 12/Fs 9/Fs 5/Fs 1 20 10 105/Fs 0.4896 0.035 0.4896 0.025 0.2604 0.025 0 Fs dB Fs dB s Fs dB Fs dB s Fs dB Fs dB s Hz Hz Deg dB s
Symbol
Min
Typ
Max
Unit
Double-Speed Mode
Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) (-0.1 dB)
Quad-Speed Mode
Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) (-0.1 dB)
High-Pass Filter Characteristics
Frequency Response Phase Deviation Passband Ripple Filter Settling Time -3.0 dB -0.13 dB @ 20 Hz
11. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 17 to 28) are normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 12. Response shown is for Fs = 48 kHz.
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CS5346 DC ELECTRICAL CHARACTERISTICS
AGND = DGND = 0 V, all voltages with respect to ground. MCLK=12.288 MHz; Fs=48 kHz; Master Mode. Parameter
Power Supply Current (Normal Operation) Power Supply Current (Power-Down Mode) (Note 13) Power Consumption (Normal Operation) (Power-Down Mode) VA = 5 V VD, VLS, VLC = 3.3 V VA = 5 V VLS, VLC, VD = 3.3 V VA = 5 V VD, VLS, VLC = 3.3 V VA = 5V; VD, VLS, VLC = 3.3 V (Note 14)
Symbol
IA ID IA ID PSRR VQ IQ ZQ FILT+ MICBIAS IMB
Min
-
Typ
41 23 0.50 0.54 205 76 4.2 55 0.5 x VA 1 23 VA 0.8 x VA -
Max
50 28 250 93 2
Unit
mA mA mA mA mW mW mW dB VDC A k VDC VDC mA
Power Supply Rejection Ratio (1 kHz)
VQ Characteristics
Quiescent Voltage Maximum DC Current from VQ VQ Output Impedance FILT+ Nominal Voltage Microphone Bias Voltage Current from MICBIAS
13. Power-Down Mode is defines as RST = Low with all clock and data lines held static and no analog input. 14. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection Diagram.
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CS5346 DIGITAL INTERFACE CHARACTERISTICS
Test conditions (unless otherwise specified): AGND = DGND = 0 V; VLS = VLC = 3.3 V. Parameters (Note 15)
High-Level Input Voltage Serial Port Control Port Serial Port Control Port Serial Port Control Port Serial Port Control Port VIH VIH VIL VIL VOH VOH VOL VOL Iin 0.7xVLS 0.7xVLC VLS-1.0 VLC-1.0 10 ---------------LRCK
6
Symbol
Min
Typ
1 -
Max
0.3xVLS 0.3xVLC 0.4 0.4 10 -
Units
V V V V V V V V A pF s
Low-Level Input Voltage High-Level Output Voltage at Io = 2 mA Low-Level Output Voltage at Io = 2 mA Input Leakage Current Input Capacitance Minimum OVFL Active Time
15. Serial Port signals include: MCLK, SCLK, LRCK, SDOUT. Control Port signals include: SCL/CCLK, SDA/CDOUT, AD0/CS, AD1/CDIN, RST, INT, OVFL.
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CS5346 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT
Logic `0' = DGND = AGND = 0 V; Logic `1' = VLS, CL = 20 pF. (Note 16) Parameter
Sample Rate Single-Speed Mode Double-Speed Mode Quad-Speed Mode
Symbol
Fs Fs Fs fmclk tclkhl
Min
8 50 100 2.048 8 -10 0 40
Typ
50 50 50 -
Max
50 100 200 51.200 10 36 60 -
Unit
kHz kHz kHz MHz ns % % ns ns % ns
MCLK Specifications
MCLK Frequency MCLK Input Pulse Width High/Low
Master Mode
LRCK Duty Cycle SCLK Duty Cycle SCLK falling to LRCK edge SCLK falling to SDOUT valid
tslr tsdo
Slave Mode
LRCK Duty Cycle SCLK Period Single-Speed Mode tsclkw 10 -------------------( 128 )Fs 10 ----------------( 64 )Fs 10 ----------------( 64 )Fs 30 48 -10 0
9 9 9
Double-Speed Mode
tsclkw
-
-
ns
Quad-Speed Mode SCLK Pulse Width High SCLK Pulse Width Low SCLK falling to LRCK edge SCLK falling to SDOUT valid
tsclkw tsclkh tsclkl tslr tsdo
-
10 36
ns ns ns ns ns
16. See Figure 1 and Figure 2 on page 17.
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CS5346
LRCK Input t sclkh t
t SCLK Input t SDOUT
slr
sclkl
sdo
t sclkw
Figure 1. Master Mode Serial Audio Port Timing
LRCK Output
t SCLK Output t SDOUT
slr
sdo
Figure 2. Slave Mode Serial Audio Port Timing
LRCK SCLK
Channel A - Left
Channel B - Right
SDATA
MSB -1
-2
-3
-4
-5
+5 +4
+3 +2
+1 LSB
MSB -1
-2
-3
-4
+5
+4 +3
+2 +1 LSB
Figure 3. Format 0, 24-Bit Data Left-Justified
LRCK SCLK
Channel A - Left
Channel B - Right
SDATA
MSB -1
-2
-3
-4
-5
+5 +4 +3 +2 +1 LSB
MSB -1
-2
-3
-4
+5 +4 +3 +2 +1 LSB
Figure 4. Format 1, 24-Bit Data IS
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CS5346 SWITCHING CHARACTERISTICS - CONTROL PORT - IC FORMAT
Inputs: Logic 0 = DGND = AGND = 0 V, Logic 1 = VLC, CL = 30 pF. Parameter
SCL Clock Frequency RST Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL and SDA Fall Time SCL and SDA Setup Time for Stop Condition Acknowledge Delay from SCL Falling (Note 17)
Symbol
fscl tirs tbuf thdst tlow thigh tsust thdd tsud trc, trd tfc, tfd tsusp tack
Min
500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 300
Max
100 1 300 1000
Unit
kHz ns s s s s s s ns s ns s ns
17. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
RST t S to p irs S t a rt R e p e a te d S t a rt t rd t fd S to p
SDA t buf t h d st t h igh t h d st t fc t su sp
SCL t t t su d t a ck t su st t rc
lo w
hdd
Figure 5. Control Port Timing - IC Format
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CS5346 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
Inputs: Logic 0 = DGND = AGND = 0 V, Logic 1 = VLC, CL = 30 pF. Parameter
CCLK Clock Frequency RST Rising Edge to CS Falling CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time CCLK Falling to CDOUT Stable Rise Time of CDOUT Fall Time of CDOUT Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN (Note 19) (Note 19) (Note 18)
Symbol
fsck tsrs tcsh tcss tscl tsch tdsu tdh tpd tr1 tf1 tr2 tf2
Min
500 1.0 20 66 66 40 15 -
Max
6.0 50 25 25 100 100
Units
MHz ns s ns ns ns ns ns ns ns ns ns ns
18. Data must be held for sufficient time to bridge the transition time of CCLK. 19. For fsck <1 MHz.
RST
t srs
CS t css CCLK t r2 CDIN t dsu t dh t f2 t scl t sch t csh
t pd
CDOUT
Figure 6. Control Port Timing - SPI Format
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CS5346 4. TYPICAL CONNECTION DIAGRAM
+3.3V 10 F 0.1 F 0.1 F 10 F +5V
VD +3.3V to +5V 0.1 F VLS
VA
3.3 F
PGAOUTA
3.3 F
MCLK Digital Audio Capture SCLK LRCK SDOUT
PGAOUTB AIN1A AIN1B Analog Input * Analog Input * Left Analog Input 1 Right Analog Input 1
INT OVFL RST MicroController SCL/CCLK
CS5346
AIN2A AIN2B
Analog Input * Analog Input *
Left Analog Input 2 Right Analog Input 2
SDA/CDOUT AD1/CDIN AD0/CS 2 k +3.3V to +5V
See Note 1
AIN3A AIN3B
Analog Input * Analog Input *
Left Analog Input 3 Right Analog Input 3
2 k VLC 0.1 F AIN4B/MICIN2 Analog Input * Right Analog Input 4 AIN4A/MICIN1 Analog Input * Left Analog Input 4
Note 1: Resistors are required for IC control port operation
Note 2 The value of R L is dictated by the microphone carteridge.
NC NC NC NC NC NC NC NC NC
AIN5A AIN5B
Analog Input * Analog Input *
Left Analog Input 5 Right Analog Input 5
AIN6A AIN6B
Analog Input * Analog Input *
Left Analog Input 6 Right Analog Input 6
VQ VQ FILT+ 10 F 0.1 F 47 F 0.1 F AGND DGND
MICBIAS 47 F AGND * AFILTA AFILTB
RL See Note 2
* 2.2nF 2.2nF * Refer to Section 4.5
Figure 7. Typical Connection Diagram
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CS5346 5. APPLICATIONS
5.1 Recommended Power-Up Sequence
1. Hold RST low until the power supply, MCLK, and LRCK are stable. In this state, the Control Port is reset to its default settings. 2. Bring RST high. The device will remain in a low power state with the PDN bit set by default. The control port will be accessible. 3. The desired register settings can be loaded while the PDN bit remains set. 4. Clear the PDN bit to initiate the power-up sequence.
5.2
System Clocking
The CS5346 will operate at sampling frequencies from 8 kHz to 200 kHz. This range is divided into three speed modes as shown in Table 1. Mode Single-Speed Double-Speed Quad-Speed Sampling Frequency 8-50 kHz 50-100 kHz 100-200 kHz
Table 1. Speed Modes
5.2.1
Master Clock
MCLK/LRCK must maintain an integer ratio as shown in Table 2. The LRCK frequency is equal to Fs, the frequency at which audio samples for each channel are clocked out of the device. The FM bits (See "Functional Mode (Bits 7:6)" on page 31.) and the MCLK Freq bits (See "MCLK Frequency - Address 05h" on page 32.) configure the device to generate the proper clocks in Master Mode and receive the proper clocks in Slave Mode. Table 2 illustrates several standard audio sample rates and the required MCLK and LRCK frequencies.
LRCK (kHz) 32 44.1 48 64 88.2 96 128 176.4 192 Mode
MCLK (MHz) * 64x 8.1920 11.2896 12.2880 * 96x 12.2880 16.9344 18.4320 128x 8.1920 11.2896 12.2880 16.3840 22.5792 24.5760 QSM
Table 2. Common Clock Frequencies
192x 12.2880 16.9344 18.4320 24.5760 33.8680 36.8640
256x 8.1920 11.2896 12.2880 16.3840 22.5792 24.5760 32.7680 45.1584 49.1520
384x 12.2880 16.9344 18.4320 24.5760 33.8680 36.8640 DSM
512x 16.3840 22.5792 24.5760 32.7680 45.1584 49.1520 -
768x 24.5760 33.8680 36.8640 SSM
1024x 32.7680 45.1584 49.1520 -
* Only available in master mode.
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CS5346
5.2.2 Master Mode
As a clock master, LRCK and SCLK will operate as outputs. LRCK and SCLK are internally derived from MCLK with LRCK equal to Fs and SCLK equal to 64 x Fs as shown in Figure 8.
MC LK F re q B its /256 /1 /1.5 MC LK /2 /3 /4 000 001 010 011 100 /1 10 /4 /2 /128 /64 F M B its 00 01 S C LK 00 01 10 LR C K
Figure 8. Master Mode Clocking
5.2.3
Slave Mode
In Slave Mode, SCLK and LRCK operate as inputs. The Left/Right clock signal must be equal to the sample rate, Fs, and must be synchronously derived from the supplied master clock, MCLK. The serial bit clock, SCLK, must be synchronously derived from the master clock, MCLK, and be equal to 128x, 64x or 48x Fs, depending on the desired speed mode. Refer to Table 3 for required clock ratios. Single-Speed
SCLK/LRCK Ratio 48x, 64x, 128x
Double-Speed
48x, 64x
Quad-Speed
48x, 64x
Table 3. Slave Mode Serial Bit Clock Ratios
5.3
High-Pass Filter and DC Offset Calibration
When using operational amplifiers in the input circuitry driving the CS5346, a small DC offset may be driven into the A/D converter. The CS5346 includes a high-pass filter after the decimator to remove any DC offset which could result in recording a DC level, possibly yielding clicks when switching between devices in a multichannel system. The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter. If the HPFFreeze bit (See "High-Pass Filter Freeze (Bit 1)" on page 31.) is set during normal operation, the current value of the DC offset for the each channel is frozen and this DC offset will continue to be subtracted from the conversion result. This feature makes it possible to perform a system DC offset calibration by: 1. Running the CS5346 with the high-pass filter enabled until the filter settles. See the Digital Filter Characteristics section for filter settling time. 2. Disabling the high-pass filter and freezing the stored DC offset. A system calibration performed in this way will eliminate offsets anywhere in the signal path between the calibration point and the CS5346.
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CS5346
5.4 Analog Input Multiplexer, PGA, and Mic Gain
The CS5346 contains a stereo 6-to-1 analog input multiplexer followed by a programmable gain amplifier (PGA). The input multiplexer can select one of six possible stereo analog input sources and route it to the PGA. Analog inputs 4A and 4B are able to insert a +32 dB (+40x) gain stage before the input multiplexer, allowing them to be used for microphone-level signals without the need for any external gain. The PGA stage provides 12 dB (4x) adjustment in 0.5 dB steps. Figure 9 shows the architecture of the input multiplexer, PGA, and microphone gain stages.
AIN1A AIN2A AIN3A AIN4A/MICIN1 MUX
+32 dB
PGA
Out to ADC Channel A
AIN5A AIN6A Analog Input Selection Bits AIN1B AIN2B AIN3B AIN4B/MICIN2 MUX
+32 dB
Channel A PGA Gain Bits
Channel B PGA Gain Bits
PGA
Out to ADC Channel B
AIN5B AIN6B
Figure 9. Analog Input Architecture
The ""Analog Input Selection (Bits 2:0)" on page 34" outlines the bit settings necessary to control the input multiplexer and mic gain. "Channel B PGA Control - Address 07h" on page 32 and "Channel A PGA Control - Address 08h" on page 33 outline the register settings necessary to control the PGA. By default, linelevel input 1 is selected, and the PGA is set to 0 dB.
5.5
Input Connections
The analog modulator samples the input at 6.144 MHz (MCLK=12.288 MHz). The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which are (n x 6.144 MHz) the digital passband frequency, where n=0,1,2,... Refer to the Typical Connection Diagram for the recommended analog input circuit that will attenuate noise energy at 6.144 MHz. The use of capacitors which have a large voltage coefficient (such as general-purpose ceramics) must be avoided since these can degrade signal linearity. Any unused analog input pairs should be left unconnected.
5.5.1
Analog Input Configuration for 1 VRMS Input Levels
The CS5346 PGA, excluding the input multiplexer, is shown in Figure 10 with nominal component values. Interfacing to this circuit is a relatively simple matter and several options are available. The simplest option is shown in Figure 11. However, it may be advantageous in some applications to provide a low-pass filter prior to the PGA to prevent radio frequency interference within the amplifier. The circuit shown in Figure 12
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CS5346
demonstrates a simple solution. The 1800 pF capacitors in the low-pass filter should be C0G or equivalent to avoid distortion issues
CS5346
36 k 9 k to 144 k
Analog Input A/ D Input V CM
+
Figure 10. CS5346 PGA
CS5346
36 k
9 k to 144 k
Analog Input
2. 2 F 100 k
A/ D Input V CM
+
Figure 11. 1 VRMS Input Circuit
.
CS5346
36 k 9 k to 144 k
Analog Input
100 100 k 2. 2 F 1800 pF
A/ D Input V CM
+
Figure 12. 1 VRMS Input Circuit with RF Filtering
5.5.2
Analog Input Configuration for 2 VRMS Input Levels
The CS5346 can also be easily configured to support an external 2 VRMS input signal, as shown in Figure 13. In this configuration, the 2 VRMS input signal is attenuated to 1.5 VRMS at the analog input with the external 12 k resistor and the input impedance to the network is increased to 48 k. The PGA gain must also be configured to attenuate the 1.5 VRMS at the input pin to the 1.0 VRMS maximum A/D input level to prevent clipping in the ADC.
CS5346
36 k 9 k to 144 k
Analog Input
12 k 100 k 2. 2 F 18 pF
A/ D Input V CM
+
Figure 13. 2 VRMS Input Circuit
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CS5346
5.6 PGA Auxiliary Analog Output
The CS5346 includes an auxiliary analog output through the PGAOUT pins. These pins can be configured to output the analog input to the ADC as selected by the input MUX and gained or attenuated with the PGA, or alternatively, they may be set to high impedance. See the "PGAOut Source Select (Bit 6)" on page 32 for information on configuring the PGA auxiliary analog output. The PGA auxiliary analog output can source very little current. As current from the PGAOUT pins increases, distortion will increase. For this reason, a high-input impedance buffer must be used on the PGAOUT pins to achieve full performance. An example buffer for PGAOUT is provided on the CDB5346 for reference. Refer to the table in "DC Electrical Characteristics" on page 14 for acceptable loading conditions.
5.7
Control Port Description and Timing
The control port is used to access the registers, allowing the CS5346 to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect to the audio sample rates. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port has two modes: SPI and IC, with the CS5346 acting as a slave device. SPI Mode is selected if there is a high-to-low transition on the AD0/CS pin, after the RST pin has been brought high. IC Mode is selected by connecting the AD0/CS pin through a resistor to VLC or DGND, thereby permanently selecting the desired AD0 bit address state.
5.7.1
SPI Mode
In SPI Mode, CS is the chip-select signal; CCLK is the control port bit clock (input into the CS5346 from the microcontroller); CDIN is the input data line from the microcontroller; CDOUT is the output data line to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge. Figure 14 shows the operation of the control port in SPI Mode. To write to a register, bring CS low. The first seven bits on CDIN form the chip address and must be 1001111. The eighth bit is a read/write indicator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated. The next eight bits are the data that will be placed into the register designated by the MAP. During writes, the CDOUT output stays in the Hi-Z state. It may be externally pulled high or low with a 47 k resistor, if desired. To read a register, the MAP has to be set to the correct address by executing a partial write cycle which finishes (CS high) immediately after the MAP byte. To begin a read, bring CS low, send out the chip ad-
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CS5346
dress and set the read/write bit (R/W) high. The next falling edge of CCLK will clock out the MSB of the addressed register (CDOUT will leave the high-impedance state). For both read and write cycles, the memory address pointer will automatically increment following each data byte in order to facilitate block reads and writes of successive registers.
CS
CC LK C H IP ADDRESS C D IN 1001111 R/W C H IP ADDRESS LSB b y te n MSB LSB MSB LSB
MAP MSB
DATA
1001111
R/W
b y te 1 High Impedance CDOUT
MAP = Memory Address Pointer, 8 bits, MSB first
Figure 14. Control Port Timing in SPI Mode
5.7.2
IC Mode
In IC Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. There is no CS pin. Pins AD0 and AD1 form the two least-significant bits of the chip address and should be connected through a resistor to VLC or DGND as desired. The state of the pins is sensed while the CS5346 is being reset. The signal timings for a read and write cycle are shown in Figure 15 and Figure 16. A Start condition is defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS5346 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low for a write). The upper 5 bits of the 7-bit address field are fixed at 10011. To communicate with a CS5346, the chip address field, which is the first byte sent to the CS5346, should match 10011 followed by the settings of the AD1 and AD0. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read, the contents of the register pointed to by the MAP will be output. Following each data byte, the memory address pointer will automatically increment to facilitate block reads and writes of successive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the CS5346 after each input byte is read, and is input to the CS5346 from the microcontroller after each transmitted byte.
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
19
24 25 26 27 28
SCL
CHIP ADDRESS (WRITE) MAP BYTE
6 6 5 4 3 2 1 0 7
DATA
6 1 0 7
DATA +1
6 1 0 7
DATA +n
6 1 0
SDA
START
1
0
0
1
1 AD1 AD0 0
ACK
ACK
ACK
ACK STOP
Figure 15. Control Port Timing, IC Write
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CS5346
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
SCL
CHIP ADDRESS (WRITE) MAP BYTE
7 6 5 4 3 2 1 0
STOP
1
CHIP ADDRESS (READ)
0 0 1 1 AD1 AD0 1
DATA
7 0
DATA +1
7 0
DATA + n
7 0
SDA
1
0
0
1
1 AD1 AD0 0
ACK START
ACK START
ACK
ACK
NO ACK
STOP
Figure 16. Control Port Timing, IC Read
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown in Figure 16, the write operation is aborted after the acknowledge for the MAP byte by sending a stop condition. The following pseudocode illustrates an aborted write operation followed by a read operation. * Send start condition. * Send 10011xx0 (chip address & write operation). * Receive acknowledge bit. * Send MAP byte. * Receive acknowledge bit. * Send stop condition, aborting write. * Send start condition. * Send 10011xx1(chip address & read operation). * Receive acknowledge bit. * Receive byte, contents of selected register. * Send acknowledge bit. * Send stop condition.
5.8
Interrupts and Overflow
The CS5346 has a comprehensive interrupt capability. The INT output pin is intended to drive the interrupt input pin on the host microcontroller. The INT pin may function as either an active high CMOS driver or an active-low, open-drain driver (see "Active High/Low (Bit 0)" on page 35). When configured as active low open-drain, the INT pin has no active pull-up transistor, allowing it to be used for wired-OR hook-ups with multiple peripherals connected to the microcontroller interrupt input pin. In this configuration, an external pull-up resistor must be placed on the INT pin for proper operation. Many conditions can cause an interrupt, as listed in the interrupt status register descriptions (see "Interrupt Status - Address 0Dh" on page 35). Each source may be masked off through mask register bits. In addition, Each source may be set to rising edge, falling edge, or level-sensitive. Combined with the option of level-sensitive or edge-sensitive modes within the microcontroller, many different configurations are possible, depending on the needs of the equipment designer. The CS5346 also has a dedicated overflow output. The OVFL pin functions as active low open drain and has no active pull-up transistor, thereby requiring an external pull-up resistor. The OVFL pin outputs an OR of the ADCOverflow and ADCUnderflow conditions available in the Interrupt Status register; however, these conditions do not need to be unmasked for proper operation of the OVFL pin.
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CS5346
5.9 Reset
When RST is low, the CS5346 enters a low-power mode and all internal states are reset, including the control port and registers, the outputs are muted. When RST is high, the control port becomes operational, and the desired settings should be loaded into the control registers. Writing a 0 to the PDN bit in the Power Control register will then cause the part to leave the low-power state and begin operation. The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either through the application of power or by setting the RST pin high. However, the voltage reference will take much longer to reach a final value due to the presence of external capacitance on the FILT+ pin. During this voltage reference ramp delay, SDOUT will be automatically muted. It is recommended that RST be activated if the analog or digital supplies drop below the recommended operating condition to prevent power-glitch-related issues.
5.10
Synchronization of Multiple Devices
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To ensure synchronous sampling, the master clocks and left/right clocks must be the same for all of the CS5346s in the system. If only one master clock source is needed, one solution is to place one CS5346 in Master Mode, and slave all of the other CS5346s to the one master. If multiple master clock sources are needed, a possible solution would be to supply all clocks from the same external source and time the CS5346 reset with the inactive edge of master clock. This will ensure that all converters begin sampling on the same clock edge.
5.11
Grounding and Power Supply Decoupling
As with any high-resolution converter, the CS5346 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 7 shows the recommended power arrangements, with VA connected to a clean supply. VD, which powers the digital filter, may be run from the system logic supplies (VLS or VLC). Power supply decoupling capacitors should be as near to the CS5346 as possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 F, must be positioned to minimize the electrical path from FILT+ and AGND. The CS5346 evaluation board demonstrates the optimum layout and power supply arrangements. To minimize digital noise, connect the CS5346 digital outputs only to CMOS inputs.
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CS5346 6. REGISTER QUICK REFERENCE
This table shows the register names and their associated default values. Addr
01h pg. 30 02h pg. 30 03h 04h pg. 31 05h pg. 32 06h pg. 32 07h pg. 32 08h pg. 33 09h pg. 33 0Ah - Reserved 0Bh 0Ch pg. 34 0Dh pg. 34 0Eh pg. 35 0Fh pg. 35 10h pg. 35 Interrupt Mode LSB Interrupt Mode MSB Interrupt Mask Active Level Control Analog Input Control PGA Ch A Gain Control PGA Ch B Gain Control PGAOut Control MCLK Frequency Reserved ADC Control Power Control
Function
Chip ID
7
PART3 1 Freeze 0 0 FM1 0 Reserved 0 Reserved 0
6
PART2 1 0 0 FM0 0 MCLK Freq2 0 PGAOut 1
5
PART1 0 0 0 Reserved 0 MCLK Freq1 0
4
PART0 0 0 0 DIF 0 MCLK Freq0 0
3
REV3 x PDN_MIC 0 Reserved 1 Reserved 0 Reserved 0 Reserved 0 Gain3 0 Gain3 0 PGAZero 1 Reserved 0 Reserved 0 ClkErr 0 ClkErrM 0 ClkErr1 0 ClkErr0 0
2
REV2 x PDN_ADC 0 Reserved 0 Mute 0 Reserved 0 Reserved 0 Gain2 0 Gain2 0 Sel2 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0
1
REV1 x Reserved 0 Reserved 0 HPFFreeze 0 Reserved 0 Reserved 0 Gain1 0 Gain1 0 Sel1 0 Reserved 0 Reserved 0 Ovfl 0 OvflM 0 Ovfl1 0 Ovfl0 0
0
REV0 x PDN 1 Reserved 0 M/S 0 Reserved 0 Reserved 0 Gain0 0 Gain0 0 Sel0 1 Reserved 0 Active_H/L 0 Undrfl 0 UndrflM 0 Undrfl1 0 Undrfl0 0
Reserved Reserved Reserved
Reserved Reserved Reserved Reserved
Reserved Reserved 0 Gain5 0 Gain5 0 0 Gain4 0 Gain4 0 PGASoft 1
Reserved Reserved 0 0
Reserved Reserved 0 0
Reserved Reserved Reserved 0 0 0
Reserved Reserved Reserved Reserved 0 0 0 0
Reserved Reserved Reserved Reserved 1 0 0 1 0 0 0 0 0 0 0 0
Interrupt Status Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 0 0 0
Reserved Reserved Reserved Reserved 0 0 0 0
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CS5346 7. REGISTER DESCRIPTION
7.1 Chip ID - Register 01h
7 PART3 6 PART2 5 PART1 4 PART0 3 REV3 2 REV2 1 REV1 0 REV0
Function: This register is Read-Only. Bits 7 through 4 are the part number ID, which is 1100b, and the remaining bits (3 through 0) indicate the device revision as shown in Table 4 below. REV[3:0]
0000 Table 4. Device Revision
Revision
A1
7.2
Power Control - Address 02h
7 Freeze 6 Reserved 5 Reserved 4 Reserved 3 PDN_MIC 2 PDN_ADC 1 Reserved 0 PDN
7.2.1
Freeze (Bit 7)
Function: This function allows modifications to be made to certain control port bits without the changes taking effect until the Freeze bit is disabled. To make multiple changes to these bits take effect simultaneously, set the Freeze bit, make all changes, then clear the Freeze bit. The bits affected by the Freeze function are listed in Table 5. Name
Mute Gain[5:0] Gain[5:0]
Register
04h 07h 08h Table 5. Freeze-able Bits
Bit(s)
2 5:0 5:0
7.2.2
Power-Down MIC (Bit 3)
Function: The microphone preamplifier block will enter a low-power state whenever this bit is set.
7.2.3
Power-Down ADC (Bit 2)
Function: The ADC pair will remain in a reset state whenever this bit is set.
7.2.4
Power-Down Device (Bit 0)
Function: The device will enter a low-power state whenever this bit is set. The power-down bit is set by default and must be cleared before normal operation can occur. The contents of the control registers are retained when the device is in power-down.
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7.3
7 FM1
ADC Control - Address 04h
6 FM0 5 Reserved 4 DIF 3 Reserved 2 Mute 1 HPFFreeze 0 M/S
7.3.1
Functional Mode (Bits 7:6)
Function: Selects the required range of sample rates. FM1
0 0 1 1
FM0
0 1 0 1
Mode
Single-Speed Mode: 8 to 50 kHz sample rates Double-Speed Mode: 50 to 100 kHz sample rates Quad-Speed Mode: 100 to 200 kHz sample rates Reserved Table 6. Functional Mode Selection
7.3.2
Digital Interface Format (Bit 4)
Function: The required relationship between LRCK, SCLK and SDOUT is defined by the Digital Interface Format bit. The options are detailed in Table 7 and may be seen in Figure 3 and Figure 4. DIF 0 1 Description Left-Justified (default) IS
Table 7. Digital Interface Formats
Format 0 1
Figure 3 4
7.3.3
Mute (Bit 2)
Function: When this bit is set, the serial audio output of the both channels is muted.
7.3.4
High-Pass Filter Freeze (Bit 1)
Function: When this bit is set, the internal high-pass filter is disabled.The current DC offset value will be frozen and continue to be subtracted from the conversion result. See "High-Pass Filter and DC Offset Calibration" on page 22.
7.3.5
Master / Slave Mode (Bit 0)
Function: This bit selects either master or slave operation for the serial audio port. Setting this bit selects Master Mode, while clearing this bit selects Slave Mode.
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CS5346
7.4
7 Reserved
MCLK Frequency - Address 05h
6 MCLK Freq2 5 MCLK Freq1 4 MCLK Freq0 3 Reserved 2 Reserved 1 Reserved 0 Reserved
7.4.1
Master Clock Dividers (Bits 6:4)
Function: Sets the frequency of the supplied MCLK signal. See Table 8 for the appropriate settings. MCLK Divider /1 / 1.5 /2 /3 /4 Reserved Reserved MCLK Freq2 0 0 0 0 1 1 1 MCLK Freq1 0 0 1 1 0 0 1 MCLK Freq0 0 1 0 1 0 1 x
Table 8. MCLK Frequency
7.5
7
PGAOut Control - Address 06h
6 PGAOut 5 Reserved 4 Reserved 3 Reserved 2 Reserved 1 Reserved 0 Reserved
Reserved
7.5.1
PGAOut Source Select (Bit 6)
Function: This bit is used to configure the PGAOut pins to be either high impedance or PGA outputs. Refer to Table 9. PGAOut PGAOutA & PGAOutB 0 High Impedance 1 PGA Output
Table 9. PGAOut Source Selection
7.6
Channel B PGA Control - Address 07h
6 Reserved 5 Gain5 4 Gain4 3 Gain3 2 Gain2 1 Gain1 0 Gain0
7 Reserved
7.6.1
Channel B PGA Gain (Bits 5:0)
Function: See "Channel A PGA Gain (Bits 5:0)" on page 33.
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7.7 Channel A PGA Control - Address 08h
6 Reserved 5 Gain5 4 Gain4 3 Gain3 2 Gain2 1 Gain1 0 Gain0 7 Reserved
7.7.1
Channel A PGA Gain (Bits 5:0)
Function: Sets the gain or attenuation for the ADC input PGA stage. The gain may be adjusted from -12 dB to +12 dB in 0.5 dB steps. The gain bits are in two's complement with the Gain0 bit set for a 0.5 dB step. Register settings outside of the 12 dB range are reserved and must not be used. See Table 10 for example settings. Gain[5:0] 101000 000000 011000 Setting -12 dB 0 dB +12 dB
Table 10. Example Gain and Attenuation Settings
7.8
ADC Input Control - Address 09h
6 Reserved 5 Reserved 4 PGASoft 3 PGAZero 2 Sel2 1 Sel1 0 Sel0
7 Reserved
7.8.1
PGA Soft Ramp or Zero Cross Enable (Bits 4:3)
Function: Soft Ramp Enable Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. See Table 11. Zero Cross Enable Zero Cross Enable dictates that signal-level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. See Table 11. Soft Ramp and Zero Cross Enable Soft Ramp and Zero Cross Enable dictate that signal-level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. See Table 11.
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CS5346
PGASoft 0 0 1 1 PGAZeroCross 0 1 0 1 Mode Changes to affect immediately Zero Cross enabled Soft Ramp enabled Soft Ramp and Zero Cross enabled (default)
Table 11. PGA Soft Cross or Zero Cross Mode Selection
7.8.2
Analog Input Selection (Bits 2:0)
Function: These bits are used to select the input source for the PGA and ADC. Please see Table 12. Sel2 0 0 0 0 1 1 1 1 Sel1 0 0 1 1 0 0 1 1 Sel0 0 1 0 1 0 1 0 1 PGA/ADC Input Microphone-Level Inputs (+32 dB Gain Enabled) Line-Level Input Pair 1 Line-Level Input Pair 2 Line-Level Input Pair 3 Line-Level Input Pair 4 Line-Level Input Pair 5 Line-Level Input Pair 6 Reserved
Table 12. Analog Input Multiplexer Selection
7.9
7
Active Level Control - Address 0Ch
6 Reserved 5 Reserved 4 Reserved 3 Reserved 2 Reserved 1 Reserved 0 Active_H/L
Reserved
7.9.1
Active High/ Low (Bit 0)
Function: When this bit is set, the INT pin functions as an active high CMOS driver. When this bit is cleared, the INT pin functions as an active low open drain driver and will require an external pull-up resistor for proper operation.
7.10
Status - Address 0Dh
6 Reserved 5 Reserved 4 Reserved 3 ClkErr 2 Reserved 1 Ovfl 0 Undrfl
7 Reserved
For all bits in this register, a `1' means the associated condition has occurred at least once since the register was last read. A `0' means the associated condition has NOT occurred since the last reading of the register. Status bits that are masked off in the associated mask register will always be `0' in this register. This register defaults to 00h.
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CS5346
7.10.1 Clock Error (Bit 3)
Function: Indicates the occurrence of a clock error condition.
7.10.2 Overflow (Bit 1)
Function: Indicates the occurrence of an ADC overflow condition.
7.10.3 Underflow (Bit 0)
Function: Indicates the occurrence of an ADC underflow condition.
7.11
Status Mask - Address 0Eh
6 Reserved 5 Reserved 4 Reserved 3 ClkErrM 2 Reserved 1 OvflM 0 UndrflM
7 Reserved
Function: The bits of this register serve as a mask for the Status sources found in the register "Status - Address 0Dh" on page 34. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect the status register. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the status register. The bit positions align with the corresponding bits in the Status register.
7.12 7.13
Status Mode MSB - Address 0Fh Status Mode LSB - Address 10h
6 Reserved Reserved 5 Reserved Reserved 4 Reserved Reserved 3 ClkErr1 ClkErr0 2 Reserved Reserved 1 Ovfl1 Ovfl0 0 Undrfl1 Undrfl0
7 Reserved Reserved
Function: The two Status Mode registers form a 2-bit code for each Status register function. There are three ways to update the Status register in accordance with the status condition. In the Rising-Edge Active Mode, the status bit becomes active on the arrival of the condition. In the Falling-Edge Active Mode, the status bit becomes active on the removal of the condition. In Level-Active Mode, the status bit is active during the condition. 00 - Rising edge active 01 - Falling edge active 10 - Level active 11 - Reserved
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CS5346 8. PARAMETER DEFINITIONS
Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Drift The change in gain value with temperature. Units in ppm/C.
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CS5346 9. FILTER PLOTS
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.40 0.42 0.44
Amplitude (dB)
Amplitude (dB)
0.46 0.48 0.50
0.52
0.54
0.56
0.58
0.60
Frequency (norm alized to Fs)
Frequency (norm alized to Fs)
Figure 17. Single-Speed Stopband Rejection
Figure 18. Single-Speed Stopband Rejection
0 -1 -2
0.10 0.08 0.06
Amplitude (dB)
Amplitude (dB)
-3 -4 -5 -6 -7 -8 -9 -10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55
0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Frequency (norm alized to Fs)
Frequency (norm alized to Fs)
Figure 19. Single-Speed Transition Band (Detail)
Figure 20. Single-Speed Passband Ripple
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.40 0.42 0.44
Amplitude (dB)
Amplitude (dB)
0.46 0.48 0.50
0.52
0.54
0.56
0.58
0.60
Frequency (norm alized to Fs)
Frequency (norm alized to Fs)
Figure 21. Double-Speed Stopband Rejection
Figure 22. Double-Speed Stopband Rejection
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CS5346
0 -1 -2
0.10 0.08 0.06
Amplitude (dB)
-3 -4 -5 -6 -7 -8 -9 -10 0.46 0.47 0.48 0.49 0.50 0.51 0.52
Amplitude (dB)
0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Frequency (norm alized to Fs)
Frequency (norm alized to Fs)
Figure 23. Double-Speed Transition Band (Detail)
Figure 24. Double-Speed Passband Ripple
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140
0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85
Amplitude (dB)
Frequency (norm alized to Fs)
Amplitude (dB)
Frequency (norm alized to Fs)
Figure 25. Quad-Speed Stopband Rejection
Figure 26. Quad-Speed Stopband Rejection
0 -1 -2 0.10 0.08 0.06
Amplitude (dB)
-3
Amplitude (dB)
0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
-4 -5 -6 -7 -8 -9 -10 0.10
0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 0.00 0.03 0.05 0.08 0.10 0.13 0.15 0.18 0.20 0.23 0.25 0.28
Frequency (norm alized to Fs)
Frequency (norm alized to Fs)
Figure 27. Quad-Speed Transition Band (Detail)
Figure 28. Quad-Speed Passband Ripple
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CS5346 10.PACKAGE DIMENSIONS 48L LQFP PACKAGE DRAWING
E E1
D D1
1
e
B A A1
L
INCHES NOM MAX MIN 0.055 0.063 --0.004 0.006 0.05 0.009 0.011 0.17 0.354 0.366 8.70 0.28 0.280 6.90 0.354 0.366 8.70 0.28 0.280 6.90 0.020 0.024 0.40 0.24 0.030 0.45 4 7.000 0.00 *Controlling dimension is mm. MILLIMETERS NOM MAX 1.40 1.60 0.10 0.15 0.22 0.27 9.0 BSC 9.30 7.0 BSC 7.10 9.0 BSC 9.30 7.0 BSC 7.10 0.50 BSC 0.60 0.60 0.75 4 7.00 *JEDEC Designation: MS022
MIN --0.002 0.007 0.343 0.272 0.343 0.272 0.016 0.018 0.000 * Nominal pin pitch is 0.50 mm
DIM A A1 B D D1 E E1 e* L
11.THERMAL CHARACTERISTICS AND SPECIFICATIONS
Parameters
Package Thermal Resistance (Note 1) Allowable Junction Temperature 48-LQFP
Symbol
JA JC
Min
-
Typ
48 15 -
Max
125
Units
C/Watt C/Watt
C
1. JA is specified according to JEDEC specifications for multi-layer PCBs. DS861PP1 39
CS5346 12.ORDERING INFORMATION
Product
CS5346 CS5346 CDB5346
Description
24-bit, 192 kHz Stereo Audio ADC 24-bit, 192 kHz Stereo Audio ADC
Package Pb-Free
48-LQFP 48-LQFP Yes Yes No
Grade
Commercial Automotive -
Temp Range
-40 to +85 C -40 to +105 C -
Container
Tray Tape & Reel Tray Tape & Reel -
Order #
CS5346-CQZ CS5346-CQZR CS5346-DQZ CS5346-DQZR CDB5346
CS5346 Evaluation Board
13.REVISION HISTORY
Release
A1
PP1
Changes Advance Release -Updated Title -Added text to Section 2. on page 7 -Added V/V representations for PGA and MIC gain specifications -Updated Automotive THD+N and DNR limits -Added reference to CDB5346 in Section 5.6 on page 25
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest you, go to www.cirrus.com
IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. IC is a registered trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc.
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DS861PP1

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